C-PHY and D-PHY routing on Jetson Orin custom carrier boards — hardware design guide

MIPI CSI-2 routing failures on custom carrier boards almost never show up in electrical tests — the traces look fine on a VNA, the signal looks clean on a differential probe, and yet the camera driver won’t lock or produces intermittent errors. The failure mode is almost always a combination of lane length mismatch, via discontinuities, and stacked-up impedance errors that only manifest at the 1–2.5Gbps data rates used in production.

Key Insights

• Length matching is more critical than absolute trace length — intra-pair skew (between + and - of a differential pair) must be < 5mm; inter-lane skew (between data lanes) must be < 10mm
• Vias destroy impedance continuity — each via adds 0.5–1pF capacitance; minimize vias on MIPI lanes, and back-drill or use microvia stacks if vias are unavoidable
• Reference plane continuity matters — do not route MIPI traces over split or interrupted ground planes; every gap in the reference plane causes a localized impedance change
• C-PHY requires symmetrical 3-conductor routing — all three conductors in a trio must be identical in length and impedance; asymmetry degrades the eye opening
• The Jetson module connector defines the impedance reference — traces must maintain 100Ω differential from the module connector to the camera connector with no discontinuities

D-PHY lane structure

Jetson Orin Module
(CSI0, 4 lanes)
  │
  ├── CLK_P / CLK_N    (clock lane, differential pair)
  ├── DATA0_P / DATA0_N (data lane 0)
  ├── DATA1_P / DATA1_N (data lane 1)
  ├── DATA2_P / DATA2_N (data lane 2)
  └── DATA3_P / DATA3_N (data lane 3)
         │
         │  ← PCB traces (must maintain 100Ω differential)
         │
  Camera connector / flex

C-PHY trio structure

Jetson Orin Module
(CSI0, 3 trios = 6 lanes equivalent)
  │
  ├── TRIO0_A / TRIO0_B / TRIO0_C   (3 conductors per trio)
  ├── TRIO1_A / TRIO1_B / TRIO1_C
  └── TRIO2_A / TRIO2_B / TRIO2_C
         │
         │  ← PCB traces (60Ω single-ended each conductor)
         │
  Camera connector

PCB stackup recommendation

For a 4-layer carrier board carrying MIPI signals:

Layer 1: Signal (MIPI traces, component side)
Layer 2: Ground plane (continuous, no splits under MIPI)
Layer 3: Power planes (split OK, away from MIPI)
Layer 4: Signal (other signals, opposite side)

Target trace parameters (FR4, 4-layer, 1oz copper):

• Trace width: 0.1mm (4 mil)
• Trace spacing: 0.1mm intra-pair, 0.3mm inter-pair
• Differential impedance: 100Ω ± 10%

For 6-layer boards with blind/buried vias (recommended for multi-CSI carrier boards):

Layer 1: Signal (MIPI)
Layer 2: Ground
Layer 3: Signal (other)
Layer 4: Ground
Layer 5: Power
Layer 6: Signal (other)

Length matching rules

Constraint	Required tolerance	Notes
Intra-pair (P vs N)	< 5mm	Use serpentine near the connector
Inter-lane (DATA0 vs DATA1 vs …)	< 10mm	Clock and data can differ more
Clock vs data (D-PHY)	< 20mm	Clock is recovered separately
C-PHY trio conductors (A, B, C)	< 2mm	Tighter than D-PHY due to trio encoding

Good: serpentine length-matching on the P trace to match N
┌──────────────────────────────────────────────────┐
│  DATA0_P: ─────────────────────────────────────  │
│  DATA0_N: ─────┬──┬───────────────────────────  │
│                └──┘ (serpentine adds ~3mm)        │
└──────────────────────────────────────────────────┘

Bad: sharp bends on differential pairs
DATA0_P: ───────┐     (adds stub and impedance change)
                └──────
DATA0_N: ─────────────

Via minimization

Each via on a MIPI lane adds capacitance that causes a local impedance dip. At 2.5Gbps:

• 0 vias: minimal signal degradation
• 1 via per lane: ~0.5–1% reflections (usually acceptable)
• 2+ vias per lane: significant eye closure, increased BER

If vias are unavoidable:

1. Use microvia stacks (buried/blind) instead of through-hole vias — smaller capacitance
2. Back-drill through-hole vias to remove the stub below the exit layer
3. Place vias in pairs (one on P, one on N at the same location) to maintain pair balance

Connector selection

Connector type	Max data rate	Notes
Molex FPC 0.5mm pitch	2.5Gbps/lane	Standard for sensor flex connections
Hirose FH52 0.5mm	2.5Gbps/lane	Lower profile than Molex
JAE FI-XB 0.3mm	4Gbps/lane	Higher density, harder to assemble
Board-to-board (Samtec)	6Gbps+	For rigid PCB-to-PCB MIPI

For CSI-2 connections requiring hot-pluggable or field-replaceable cameras, avoid standard FPC connectors — they are not rated for frequent insertion cycles. Use a locking FFC connector rated for 50+ cycles minimum.

Common routing mistakes and fixes

Mistake	Effect	Fix
Routing MIPI over split ground plane	Impedance spike at gap, reflections	Move split plane gap away from MIPI traces
Asymmetric intra-pair length (> 10mm)	Phase error, reduced noise margin	Serpentine the shorter trace
Via under differential pair (not both)	Single-ended spike	Via both P and N at same location
90° bends on differential pairs	Impedance mismatch at corner	Use 45° bends or curved routing
Pull-up/pull-down resistors on MIPI lines	Impedance distortion, DC offset	Remove — MIPI has on-die termination
Mixing layers without via pairs	Broken reference plane continuity	Keep MIPI on one layer or use matched via pairs

For carrier board hardware design considerations including power sequencing and connector placement, see Jetson carrier board hardware design mistakes to avoid. For enabling the CSI interface in device tree after hardware bring-up, see How to enable CSI0 on Jetson Orin.

FAQ

What is the difference between C-PHY and D-PHY for Jetson Orin camera interfaces?

D-PHY uses differential pairs (clock + data lanes). C-PHY uses 3-wire trios that encode clock and data together, achieving higher bandwidth per pin. Jetson Orin AGX supports both. Most camera sensors use D-PHY; choose based on your sensor’s physical interface.

What trace impedance should I use for MIPI D-PHY on a Jetson carrier board?

100Ω differential (50Ω each trace to ground). For C-PHY, 60Ω single-ended per conductor. Tolerance: ±10%.

How long can MIPI traces be on a Jetson carrier board?

Under 150mm for rates above 1Gbps, under 100mm for 2.5Gbps lanes on standard FR4. Use low-loss PCB material for longer runs.

Do I need termination resistors on MIPI D-PHY lanes on a carrier board?

No. Both Jetson NVCSI and standard camera sensors have on-die 100Ω differential termination. Adding external resistors creates impedance discontinuities.

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